Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels in view of applications to the vertex detector at the SuperB Factory. The circuits have been designed in a 130 nm CMOS, vertical integration technology, which may provide some advantages in terms of functional density and electrical isolation between the analog and the digital section of the front-end. The paper discusses the main features of the two channels, with emphasis on some specific problems and their solution through purposely devised blocks and suitable design criteria.