Design of a Pixel Readout Processor for Nano-meter Resolution X-ray Ptychography

High-luminosity beamlines have been used vastly as a source for the perpetual investigation of the structure of matter. Progressing towards new generations of light storage rings, the specifications on the detectors and front-end mixed-signal electronics have become more and more stringent requiring dedicated studies and exploiting every aspect of the integrated circuit technologies. In the present book an introduction to the basics of radiation interaction with matter and synchrotron systems will be provided to introduce x-ray ptychography, the target application of the developed application specific integrated circuit, pFREYA16. The core of the work will be focused on 1) motivating the development of such a circuit, in the frame of an international collaboration with Argonne National Laboratory (Chicago, IL, US) and the University of Pavia for the development of a top-tier, 1-MHz frame, pixellated detector for nano-meter resolution x- ray ptychography applications, and on 2) analysing each analog and digital block integrated into the produced chips, reporting post-layout simulations and considerations for each of them. The ASIC has been developed in a commercial 65 nm CMOS technology and it is a pixellated readout circuit composed of very low noise and low power pixels. In post-layout simulations, each pixel has reported a single photon detection capability, with an equivalent noise charge of 250 electrons rms, power consumption of 220 µW/pixel, and an input dynamic range of up to 256 photons with three different photon energies: 5 keV, 9 keV, and 25 keV. Each pixel is configurable with variable integration time, four CSA modes, and four selectable peaking times. It also integrates a signal over threshold detection chain to reject unwanted signals and a 10-bit SAR ADC to digitise the output.