Time invariant analog processors for monolithic deep n-well CMOS pixel detectors

This work is concerned with the design of time invariant analog circuits for processing the signals from deep n-well monolithic CMOS sensors. As compared to the three-transistor front-end typically used in imaging applications, the schemes proposed here, which were conceived to be included in a binary readout channel, lend themselves to pixel-level sparsified readout and are expected to be capable of managing the large flow of data anticipated for the future high luminosity colliding machines. Various solutions complying with different power dissipation and point resolution constraints have been implemented in a 130 nm CMOS technology, paying particular attention to equivalent noise charge and threshold dispersion performance. This paper intends to describe and compare the features of the different approaches by means of theoretical analysis, simulation and experimental results.