First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named SDR0 (Sparsified Digital Readout), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors.
In this work, the experimental characterization of the SDR0 chip, including data from radioactive source (55Fe) tests, will be presented.