Design and test of clock distribution circuits for the Macro Pixel ASIC

Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the High Luminosity LHC. A test chip including low power clock distribution circuits of the MPA has been designed in a 65. nm CMOS technology and thoroughly tested. This work summarizes the experimental results relevant to the prototype chip, focusing particularly on the power and speed performance and compares such results with those coming from circuit simulations.