Proposal of a sparsification circuit for mixed-mode MAPS detectors

This paper shows the design of a new mixed-mode chip built up of a bidimensional matrix of Monolithic Active Pixel Sensor (MAPS), and of an off-pixel digital readout sparsification circuit. The mixed-mode approach extends the performance of the chip as both the matrix and the readout logic have been developed separately. In particular, the matrix of MAPS has been described with a VHDL model and used as a macro-cell block within a bigger digital design that includes the readout logic. The global place-and-route has been also digitally carried out. The design was submitted via the STM 0.13 um CMOS technology and readout logic is based on standard cells by implementing an optimized token-like technique. The proposed fast readout architecture should extend the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors. The design, which has been developed within the SLIM5 Collaboration, is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments.