Heavy-Ions induced SEE effects measurements for the STRURED ASIC

With the aim of developing a radiation-tolerant circuit, a digital test microelectronic device has been designed and fabricated by using a standard-cell library of a 130-nm CMOS technology, including three different architectures to correct circuit malfunctions induced by the occurrence of Single-Event Effects (SEEʼs). SEEʼs are one of the main reasons of failures affecting electronic circuits operating in harsh radiation environments, such as in experiments performed at High Energy Physics (HEP) colliders or in apparatus to be operated in Space. On the same digital circuit specifically designed, three redundant architectures added to a basic scheme have been implemented in order to evaluate their effectiveness to prevent SEE. This may give an indication on their usage in future digital circuits specifically designed for the above mentioned applications. We present the results of SEE cross section measurements performed on a test digital device exposed to a high energy heavy ion beam at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova Italy).