From 65 nm to 28 nm CMOS: design of analog building blocks of frontend channels for pixel sensors in high-energy physics experiments

The 28 nm CMOS process is the major commercial successor of the 65 nm one and widely used for the design of advanced application-specific integrated circuits (ASICs) in the field of instrumentation for radiation detectors in high-energy physics (HEP) experiments. The HEP community is now migrating to the 28 nm process for the design of readout electronics for pixel detectors and other mixed-signal circuits. In this work a comparison of the main device parameters, including noise, intrinsic gain and mismatch, will be presented for the two technologies. The design in 28 nm CMOS of basic analog building blocks for the development of pixel frontend channels will also be discussed. In particular, this work will be focused on the design of compact gain stages for the design of charge-sensitive amplifiers and on the development of fast- and low-power asynchronous comparators.