Threshold tuning DACs for pixel readout chips at the High Luminosity LHC

This work is concerned with the design and the characterization of digital-to-analog current converters, developed in a 65 nm CMOS technology, conceived for threshold tuning of front-end channels at the High-Luminosity LHC experiment upgrades. Two DAC designs were integrated in a small prototype chip, that was submitted in August 2018 in the framework of the RD53 developments. One of the DAC designs features a binary weighted architecture implemented with cascoded current mirrors and no dummy transistors, whereas the second one, sharing the same architecture, exploits regular current mirrors with dummy transistors. The prototype has been tested before and after exposure to X-rays up to a TID of 460 Mrad(SiO2). The main performance parameters of the two structures, namely DAC dynamic range, INL and DNL, are compared and discussed in the paper.