Review of radiation effects leading to noise performance degradation in 100-nm scale microelectronic technologies

Advanced CMOS technologies promise to meet the demanding requirements of mixed-signal integrated circuits for detector readout in future experiments at SLHC, ILC and Super B Factory. In the particle physics community, microelectronics designers are presently evaluating CMOS processes with a minimum feature size in the 100 nm range. One of the key issues is noise performance and its degradation with exposure to high doses of ionizing radiation, as it is expected in the innermost detector layers of SLHC. This paper presents a comprehensive analysis of total dose damage mechanisms in 90 nm and 130 nm CMOS transistors and of their impact on the noise behavior of analog blocks. Modeling of radiation effects in these devices is used to define rad-hard design criteria.