Design optimization of charge preamplifiers with CMOS processes in the 100 nm gate length regime

Low noise design of charge sensitive amplifiers in deep submicron CMOS technologies is discussed based on the experimental characterization of transistors belonging to a 130 nm and a 90 nm minimum channel length processes. After briefly examining the main preamplifier noise sources, residing in the input element, achievable resolution limits in charge measuring systems employing such technologies are discussed under different detector capacitance, processing time and power dissipation constraints. The equivalent noise charge (ENC) model adopted in this work takes into account the behavior of series 1/f noise as a function of the overdrive voltage in PMOS devices. Moreover, noise in the gate current, whose effects could be neglected in past CMOS technologies featuring larger gate oxide thickness, is shown to play a role in the optimization process, significantly affecting the preamplifier performance at long shaping times. The extent of this contribution, besides depending on the drain current in the input device, is also determined by its drain voltage, which therefore may become a critical parameter in the design of low noise analog blocks.