Heavily irradiated 65-nm readout chip with asynchronous channels for future pixel detectors

This paper discusses the main results relevant to the characterization of an analog front-end processor designed in view of experiments with unprecedented particle rates and radiation levels at the high-luminosity Large Hadron Collider (HL-LHC). The front-end channel presented in this paper is part of the CHIPIX65-FE0 prototype, a readout application-specified integrated circuit designed in a 65-nm CMOS technology in the frame of the CERN RD53 collaboration. The prototype integrates a 64 × 64 pixel matrix, divided into two 32 × 64 submatrices, featuring squared pixels with 50- μm pitch, embodying two analog front-end architectures based on synchronous and asynchronous hit discriminators. This paper is focused on the characterization of the array with asynchronous channels, before and after exposure to ionizing doses up to 630 Mrad(SiO2) of X-rays. The analog chain takes a per-channel area close to 1000 μm2, with a power dissipation of around 5 μW. The mean value of the equivalent noise charge, not significantly affected by radiation, is close to 100 electrons with no sensor connected to the front end. The threshold dispersion before irradiation is 55 electrons, for a tuned threshold of 600 electrons, with a moderate increase after irradiation. In-pixel analog-to-digital conversion, based on the time-over-threshold technique, is not appreciably influenced by the radiation as well. The assessed performance guarantees sub-1000 electrons stable threshold operations, which is a mandatory feature for highly efficient readout chips at the HL-LHC.